Research Associate

Yi Shan

Title:  Associate Professor
Subject:  Microelectronics
Phone: +86-021-62511070
Fax: +86-021-62524192
Email:  yishan@mail.sim.ac.cn
Address: 865 Changning Road, Shanghai,China, 200050

Resume

Yi Shan, Ph.D, senior engineer of Shanghai Institute of Microsystem and Information Technology (SIMIT). He earned his Ph.D degree in Microelectronics from SIMIT. His researches focus on semiconductor device and IC design. He has published more than 10 peer-reviewed papers and obtained 7 authorized US invention patents with more than 36 authorized China invention patents.

 

EDUCATION

B.S., Electronic Engineering, Southeast University

Ph.D., Microelectronics, SIMIT

 

RESEARCH EXPERIENCE 

Principal Engineer, Design Service Department, HHGRACE, 2004-2010;

Principal Engineer, Technology Development Department, GLOBALFOUNDRIES, 2010-2012;

Manager, Technology Development Department, XMC, 2014-2017

  

SELECTED PUBLICATIONS

1. Yi Shan, Jun He, Jian Hu, Jian Liu and Wen Huang, “NLDD/PHALO Assisted Low-Trigger SCR for High-Voltage Tolerant ESD Protection without Using Extra Masks,” IEEE Electron Device Letter, vol. 30, NO. 7, 2009.

2. Yi Shan, Jun He and Wen Huang, “New Substrate-Triggered ESD Protection Structures in a 0.18-μm CMOS Process without Extra Mask,” Microelectronic Reliability, vol. 49, Jan. 2009, pp. 17-25.

3. Mo Zhou, Yi Shan, Yemin Dong, An Enhanced Well-Changed GGNMOS for 3.3-V ESD Protection in 0.13-μm SOI Process, IEICE Trans. Electron, Vol. E103-C, No.6 June 2020;

4. Zhenwei Zhang, Yi Shan, Yemin Dong, A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration, IEICE Electronics Express, Vol.17, No.10, 1-6, 2020;

5. Zhenwei Zhang, Lei Qiu, Yi Shan, Yemin Dong, A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure, IEICE Electronics Express, Vol.17, No.10, 1-6, 2020;

6. Zhuojun Chen, Ding Ding, Yemin Dong, Yi Shan, Yun Zeng, Jiantou Gao, Design of a High-performance Low-cost Radiation-Hardened Phase-Locked Loop for Space Application, IEEE Transactions on Aerospace and Electronic Systems, 2020

 

SELECTED PATENTS

1. Yi Shan, Jun He, “Thyristor comprising a special doped region characterized by an LDD region and a halo implant,” US patent NO. 8703547.

2. Yi Shan, Dawei Lai, Manjunatha Prabhu, “ESD protection for high voltage applications,” US patent NO. 9343413.

3. Yi Shan, Manjunatha Prabhu, “Method and apparatus for ESD circuits,” US patent NO. 8885305.

4. Manjunatha Prabhu, Ryan Shan, Mahadeva Natarajan, “Driver-based distributed multi-path ESD scheme,” US patent NO. 8786990.

5. Yi Shan, Yemin Dong, “An ESD protection structure”, Chinese invention patent NO. 201711223054.4

6. Yi Shan, “ESD protection circuit and 3D IC’s ESD protection circuit”, Chinese invention patent NO. 201510401741.5

7. Yi Shan, “A switch circuit and driver circuit”, Chinese invention patent NO. 201510220585.2

8. Yi Shan, “A level-shift circuit”, Chinese invention patent NO. 201010144039.2

9. Yi Shan, “I/O cell and intergrated circuit”, Chinese invention patent NO. 200910199653.6